1. Field of the Invention
The present invention relates to a silicide layer forming method employed for a semiconductor integrated circuit which is obtained by forming a number of electronic components on a substrate or the like and a semiconductor integrated circuit including a silicide layer, and more particularly, it relates to a silicide layer forming method by a salicide process employing a refractory metal silicide film for enabling a high-speed operation and attaining high reliability.
2. Description of the Background Art
An example of a general salicide (self-aligned silicide) process for forming a refractory silicide film is described with reference to FIGS. 22 to 25.
First, a well 1a, isolation oxide films 2, and an impurity layer 3 which controls a threshold voltage are formed on a silicon substrate 1. Thereafter a silicon oxide film 4 of 6.5 nm in thickness, for example, is formed on the silicon substrate 1, and a polycrystalline silicon layer for defining a gate electrode is deposited on the oxide film 4 in a thickness of 200 nm. An impurity is added to this polycrystalline silicon layer, which in turn is patterned by a photolithographic step and thereafter anisotropically etched for forming a gate electrode 5.
Then, LDD (lightly doped drain) layers 6 which are also referred to as extension layers are formed, and thereafter an oxide film is deposited by CVD (chemical vapor deposition). This oxide film is etched back by reactive ion etching (hereinafter referred to as RIE), for forming side walls 7 consisting of silicon oxide on right and left sides of the gate electrode 5.
Then, high-concentration source/drain layers 8 are formed by high-concentration ion implantation, and thereafter heat treatment is performed for activation. FIG. 22 is a sectional view showing a state after completion of the activation.
Then, the salicide process is carried out.
In the salicide process, a surface of the silicon substrate 1 is first cleaned by proper pretreatment, and thereafter a metal film 9 is deposited on the structure shown in FIG. 22 (see FIG. 23).
Then, the silicon substrate 1 shown in FIG. 23 is heated under a proper atmosphere for forming silicide films 10 by the silicon substrate 1 and the polycrystalline silicon forming the gate electrode 5 (see FIG. 24). The composition of these silicide films 10 is expressed as MSix, assuming that M represents a metal element forming the metal film 9, for example, where x represents the ratio of silicon to the metal. In this case, short-time heat treatment (rapid thermal annealing) is generally performed through a lamp annealing furnace. The heat treatment which is performed through the lamp annealing furnace immediately after deposition of the metal film 9 is hereafter referred to as first RTA.
At this time, no silicide reaction takes place on upper portions of the isolation oxide films 2 and the side walls 7 due to absence of silicon, and the unreacted metal film 9 remains at least on these upper portions (see FIG. 24). Then, the metal film 9 still containing the unreacted metal M etc. is selectively removed while leaving the silicide films 10 formed by the reacted silicide MSix (see FIG. 25). Basically, the salicide process is ended in the aforementioned step.
However, when the silicide films formed through the aforementioned process are made of titanium silicide TiSix, for example, further heat treatment is performed at a high temperature or over a long time for forming titanium silicide films of TiSi.sub.2 having a different composition or crystal structure, since the electric properties of titanium silicide (TiSix) are insufficient. Also in case of changing the composition or crystal structure of titanium silicide, short-time heat treatment is generally performed through a lamp annealing furnace. The short-time heat treatment employed for changing the composition or crystal structure of such silicide films is hereinafter referred to as second RTA. Due to the salicide process employing the aforementioned steps, an electrode can advantageously be selectively formed only on a region exposing a silicon surface on the silicon substrate 1.
In recent years, on the other hand, integrated circuits are implemented with higher density of integration such that the gate length or a silicide wire of a planar MOS transistor which is a kind of MIS transistor is refined, for example. Due to the aforementioned structure of the conventional MIS transistor fabricated through the salicide process, further, phase transition from a C49 phase to a C54 phase hardly takes place in the crystal structure even by second RTA in case of titanium silicide (TiSi.sub.2) when the gate length or the width of the silicide wire is refined to below 0.5 .mu.m, leading to such a problem that the sheet resistance of the titanium silicide films is abruptly increased. FIG. 26 shows exemplary gate dependency of gate resistance in titanium silicide (TiSi.sub.2).